1. Field of the Invention
The present invention relates to a timing controller and a Liquid Crystal Display (LCD) using the same, which compensate for the delay of a mini-Low Voltage Differential Signal (LVDS) output signal generated between the timing controller and a data drive Integrated Chip (IC).
2. Discussion of the Related Art
Recently, flat panel display devices that can decrease a weight and a volume corresponding to the limitations of Cathode Ray Tubes (CRTs) are being developed. Liquid Crystal Displays (LCDs), Plasma Display Panels (PDPs), Field Emission Displays (FEDs), and Organic Light Emitting Diodes (OLEDs) are actively being researched as flat panel display devices.
Among such display devices, LCDs have a small size, a thin thickness and low power consumption, and thus are being applied to notebook computers, office automation equipment and audio/video equipment. In addition, with the advance of a manufacture technology, LCDs are being applied even to large digital televisions (DTVs). Particularly, since an active matrix type of LCD that uses a Thin Film Transistor (TFT) as a switch device is suitable for displaying a dynamic image, the active matrix type of LCD are widely being used in various fields.
Such LCDs generally include an interface, a timing controller, a reference voltage generator, a data driver, a gate driver, a power source voltage generator, and a liquid crystal display panel.
Herein, the interface receives data (for example, RGB data) and timing signals (for example, an input clock, a horizontal sync signal, a vertical sync signal, and a data enable signal) that are inputted from a driving system such as a personal computer or a DTV System on Chip (SoC), and supplies the received data and signals to the timing controller. In this case, a Low Voltage Differential Signal (LVDS) interface and a Transistor Transistor Logic (TTL) interface are mainly being used for transferring the data and timing signals from the driving system. The interface and the timing controller are integrated in a single chip and used.
Moreover, the timing controller generates control signals for driving the data driver including a plurality of data drive integrated circuits (ICs) and the gate driver including a plurality of gate drive ICs, by using the timing signals that are inputted through the interface. Also, the timing controller transfers the data, which are inputted through the interface, to the data driver.
In devices such as notebook computers that are configured with an LCD device having the above-described basic structure, a signal (i.e., an LVDS signal) inputted from the interface is transferred to the timing controller and is transferred to the data driver through the internal circuit of the timing controller.
FIG. 1 is a block diagram schematically illustrating a related art LCD, and is an exemplary diagram for describing a method where the related art LCD compensates for the delay of a mini-LVDS output signal.
The related art LCD, as illustrated in FIG. 1, controls a mini-LVDS output current according to an RMLVDS resistance value.
That is, in the related art LCD, a timing controller 11 changes a resistance value with an external control (RMLVDS) pin to control the mini-LVDS output current, thereby controlling the output levels of total mini-LVDS output signals.
Therefore, the related art LCD may control the level of the mini-LVDS output signal with a fixed termination resistance value and an output current.
However, although the mini-LVDS outputs of the timing controller 11 are outputted identically, since the mini-LVDS outputs pass through various cables 12 and a source Printed Circuit Board (PCB) 13 that exist between the timing controller 11 and the data drive IC 15, delay occurs.
Therefore, different delays occur in the input terminals of each of the data drive ICs 15, and thus the mini-LVDS outputs may not be synchronized with a reference clock. Due to this, the output of a specific data drive IC may be abnormal.
However, the related art LCD cannot control the delay of the mini-LVDS output signal that is outputted from the timing controller to the each data drive IC.
To provide additional description, while the mini-LVDS signals outputted from the timing controller 11 are passing though the cables 12 and the source PCB 13, the mini-LVDS signals are required to have the same delay in order for the data drive ICs 15 to be synchronized with each other. For this, a cable resistance component is required to be constant, and all transfer paths in the source PCB 15 are required to match with each other. However, delay occurs substantially because it is difficult to maintain the same transfer path length on a PCB having a limited area, and moreover, it is difficult to maintain the same parasitic component between all transfer lines in the cables 12. To simply solve the above-described delay, it is required to perform delay compensation for a specific path having an error. However, the related art LCD cannot control delay. Furthermore, since improvement is required through the re-design of the source PCB 15 or the like for solving the delay of a specific path, additional development time and cost for improvement are expended.